NODE #047 UPLINK · STABLE VOL. III.04
MELBOURNE · FL

SALAH HARB.

Hardware acceleration, real-time photonic sensing, and scientific cloud — built to survive contact with the lab bench.

role
Research Fellow · CMDS · Florida Tech
prev.
LBNL · Concordia · MDA · JUST
focus
FPGA · OFDR · GPU · cloud
issued
2026.04
§ 01 / 05

//ABOUT

one paragraph · read 30s

I build low-latency systems where silicon meets physics — and data meets scientists.

I'm a Research Fellow at the Computational Mathematics & Data Science Center at Florida Institute of Technology, designing an AI-assisted, cloud-native repository for medical imaging data on AWS S3 and Databricks.

Before that I spent two years at Lawrence Berkeley National Laboratory designing a GPU-accelerated Optical Frequency Domain Reflectometry platform with custom FPGA IP on the AMD Xilinx RFSoC 4x2 — <10 ms latency for distributed fiber-optic sensing. My Ph.D. at Concordia was on secure lossless image steganography, co-designed in hardware on Zynq-7000 SoCs.

Originally from Irbid, JO; grad school in Montréal, QC; currently in Melbourne, FL. Off-hours: reading, gaming, building PCs, cooking, long drives, beach.

§ 02 / 05

//SELECTED WORK

4 representative cases
FIG. 02.01 · OFDR · DISTRIBUTED STRAIN <10 ms · CUDA · RFSoC 4x2
2024 – 2026 · LBNLCASE 02.01

Real-time GPU-accelerated OFDR with an integrated auxiliary interferometer.

End-to-end distributed fiber-optic sensing with <10 ms feedback. Custom FPGA IP on the AMD Xilinx RFSoC 4x2 — DDR4, DMA, ADC/DAC, PCIe, QSFP28 links, tunable-laser sync. Validated on fiber-under-test setups with localized and distributed heating / strain experiments.

CUDACuPyVHDLVerilogRFSoC 4x2Python / FlaskDOE · LDRD
2026 → present · Florida TechCASE 02.02

AI-assisted cloud-native medical imaging repository.

CMDS Center. Scalable storage on Amazon S3; Databricks for distributed, analysis-ready processing. Natural-language dataset discovery; extensible analytics with built-in apps and user-defined containerized pipelines under secure governance.

AWS S3DatabricksMetadataAIContainers
2019 – 2024 · PhDCASE 02.03

Hardware-accelerated steganography & crypto.

A secure, lossless modulus-based image-steganography model with pipelined FPGA realization on Zynq-7000. Reconfigurable cores for AES, ECC over GF(2ⁿ), and Paillier — optimized for real-time embedded deployment.

Zynq-7000AESECCPaillierVHDL
2022 – 2023 · MDACASE 02.04

Payload control for CanadaARM.

RTL (VHDL / Verilog) modules and verification testbenches for satellite communication and payload control — timing, redundancy, and fault-tolerance under aerospace-grade constraints.

AerospaceRTLVerificationAvionics
§ 03 / 05

//INTERESTS

16 threads · tagged
hardware acceleration fpga prototyping optical frequency domain reflectometry fiber-optic sensing gpu / cuda signal processing · fft · hilbert hpc & distributed systems image steganography aes · ecc · paillier zynq-7000 / rfsoc 4x2 / pynq high-level synthesis axi · dma · pcie wireless sensor networks m2m · 6g neural networks arithmetic circuits
§ 04 / 05

//FIELD NOTEBOOK

generative · swap w/ photos later
TILE.01
OFDR rack · LBNL
TILE.02
Fiber coil · FUT
TILE.03
RFSoC 4x2 bring-up
TILE.04
Berkeley · night
§ 05 / 05

//OFF-HOURS

non-technical

Reading, gaming, building PCs, cooking — and exploring cuisines. Middle Eastern, Italian, Thai, Japanese.