§ RESEARCH · PROJECTS · INTERESTS
研究 · プロジェクト
INTERESTS / PROJECTS
I work where hardware design, signal processing, and applied physics overlap — building systems whose latency budget is in cycles and whose error budget is in microstrain.
7research threads
9selected projects
<10 msbest latency · ofdr
2awards
§ 01
//RESEARCH INTERESTS関心領域
seven threads
- hw accel · securityPipelined, reconfigurable cryptographic cores — AES, ECC over GF(2ⁿ), Paillier — optimized for real-time embedded deployment.
- photonics · sensingOFDR, auxiliary-interferometer nonlinearity compensation, distributed fiber-optic temperature/strain sensing.
- ml & aiAI-assisted dataset discovery, extensible analytics workflows, neural-network acceleration on heterogeneous platforms.
- distributed · hpcShared-memory multiprocessing for time-critical pipelines; cloud-native scientific platforms on AWS + Databricks.
- signal processingReal-time FFT, Hilbert transform, cross-correlation, and resampling for OFDR and related sensing pipelines.
- image steganographySecure, lossless embedding with public-key and noise-based constructions, verified in hardware.
- networked systemsWireless sensor networks, M2M, and emerging 6G use-cases for IoT.
§ 02
//SELECTED PROJECTS選抜作品
chronological
2026 →
AI-Assisted Cloud-Native Medical Imaging Repository
Florida Tech · CMDS · AWS S3 · Databricks
- Scalable storage on Amazon S3 with Databricks for distributed, analysis-ready processing.
- Natural-language dataset discovery; extensible analytics with user-defined containerized pipelines.
- Metadata-driven analysis under secure governance and reproducible deployment.
2024 – 2026
High-Resolution Distributed Fiber-Optic Sensing (OFDR)
LBNL · ATAP · DOE LDRD
- GPU-accelerated pipeline (CUDA/CuPy, RTX 4070 Ti) with <10 ms latency.
- Custom FPGA IP on AMD Xilinx RFSoC 4x2 — DDR4, DMA, ADC/DAC, PCIe, QSFP28, laser sync.
- Python/Flask multiprocessing for acquisition, cross-correlation, frequency-shift analysis.
- Validated on FUT setups with localized and distributed heating/strain experiments.
2022 – 2023
Payload Control for the CanadaARM Robotic System
MDA · Satellite & Robotic Systems · Montréal
- RTL (VHDL/Verilog) for satellite communication and payload control.
- Comprehensive testbenches under aerospace timing, redundancy, and fault-tolerance constraints.
2020 – 2023
Secure Lossless Image Steganography + FPGA Realization
Concordia · PhD · Zynq-7000 APSoC
- Modulus-based secure lossless embedding scheme.
- Real-time ZedBoard prototype for enhancing digital image sizes.
- High-speed pipelined FPGA implementation — 2nd place, Grad Research Paper Competition 2022.
2020
Separable Image Steganographic Scheme via Paillier Cryptosystem
Concordia · PhD
- Reconfigurable hardware implementation under a Paillier public-key cryptosystem.
2019 – 2022
Elliptic-Curve & AES Cores for Large-Scale Embedded Systems
Concordia · PhD · GF(2ⁿ)
- High-speed EC cryptosystem with efficient projective coordinates.
- Reconfigurable high-speed AES core — ZedBoard Zynq-7000 real-time encryption prototype.
2017
Square-Root Computation over Large GF(2ᵐ)
R&D · finite-field arithmetic
- Reconfigurable, high-speed, area-efficient core.
2016 – 2017
Solid-State Drive Write Efficiency via Data Patterns
WNLO · HUST · Wuhan
- Improved SSD write time/space efficiency by leveraging data patterns.
2013 – 2014
Compact 32-bit AES Core on FPGA
JUST · M.Sc. · MicroBlaze softcore
- Reconfigurable compact AES core + real-time encryption prototype.